1. Field of the Invention
The present invention relates to the storage of curves associated with integrated circuit device functions and in particular to generating a base curve database to reduce storage cost.
2. Related Art
FIG. 1 illustrates a simplified representation of an exemplary digital integrated circuit design flow 100. At a high level, the process starts with the product idea in step 101. In designing an integrated circuit (IC), engineers typically rely upon computer-implemented tools to help create a circuit schematic design consisting of individual devices coupled together to perform a certain function. In one embodiment, these computer-implemented tools include EDA software 102, which can translate the circuit into a physical representation, i.e. a layout. When the layout is finalized, it can be used during tape-out 103. After tape out, fabrication 104 as well as packaging and assembly 105 can proceed to produce the integrated circuit (IC) 106, also called a chip.
Note that EDA software (also called EDA tools) 102 can perform a plurality of steps 110-119, which are shown in linear fashion for simplicity in FIG. 1. In an actual IC design process, various steps may be repeated until certain tests are passed. Moreover, these steps may occur in different orders and combinations. Therefore, these steps are described below for context and general explanation rather than as a specific, or recommended, design flow for a particular IC.
In step 110, engineers can describe the functionality that they want to implement in a system design, perform what-if planning to refine that functionality, and check the costs associated with the system design. Hardware-software architecture partitioning can occur in this step. Exemplary EDA software products from Synopsys, Inc. that can be used at this step include Model Architect, Saber, System Studio, and DesignWare® products.
In step 111, the VHDL or Verilog code for modules in the system design, i.e. the logic design, can be written and then verified for functional accuracy (e.g. checked to ensure that the logic design produces the correct outputs). Exemplary EDA software products from Synopsys, Inc. that can be used in step 111 include VCS, VERA, DesignWare®, Magellan, Formality, ESP and LEDA products.
In synthesis and design for test step 112, the VHDL/Verilog code can be translated to a netlist. This netlist can then be optimized for the target technology. Additionally, tests for checking the finished IC can be designed and implemented. Exemplary EDA software products from Synopsys, Inc. that can be used at this step include Design Compiler®, Physical Compiler, Test Compiler, Power Compiler, FPGA Compiler, Tetramax, and DesignWare® products.
In netlist verification step 113, the netlist can be checked for compliance with timing constraints and for correspondence with the VHDL/Verilog code. Exemplary EDA software products from Synopsys, Inc. that can be used at this step include Formality, PrimeTime, and VCS products.
In design planning step 114, an overall floorplan for the chip is constructed and analyzed for timing and top-level routing. Exemplary EDA software products from Synopsys, Inc. that can be used at this step include Astro and IC Compiler products.
In physical implementation step 115, the circuit elements of the logic design can be positioned and connected (generally called “place and route”). Exemplary EDA software products from Synopsys, Inc. that can be used in step 115 include the Astro and IC Compiler products.
In analysis and extraction step 116, the circuit function can be verified at a transistor level, thereby permitting what-if refinement. Exemplary EDA software products from Synopsys, Inc. that can be used in step 116 include AstroRail, PrimeRail, Primetime, and Star RC/XT products.
In physical verification step 117, various checking functions can be performed to ensure correctness for manufacturing, electrical issues, lithographic issues, and circuitry. Exemplary EDA software products from Synopsys, Inc. that can be used in step 117 include the Hercules product.
In resolution enhancement step 118, the layout can be manipulated to improve manufacturability of the design. Exemplary EDA software products from Synopsys, Inc. that can be used in step 118 include Proteus, ProteusAF, and PSMGen products.
In mask data preparation step 119, the “tape-out” data for production of masks for lithographic use can be generated. Exemplary EDA software products from Synopsys, Inc. that can be used in step 119 include the CATS® family of products.
Various steps described above, e.g. steps 112-116, require access to a standard cell library that includes standard cells (hereinafter called cells) as well as a database that stores certain integrated circuit (IC) information associated with those cells. This standard cell library can include thousands of cells usable in implementing an IC design. Exemplary standard cells could include flip-flops, logic gates, adders, or other IC devices commonly used in an IC design. Exemplary IC information can include cell pin capacitance, cell output delay, cell output slew, and cell output current.
FIG. 2A illustrates an exemplary standard cell 200, i.e. an inverter 201 having an output node coupled to ground via a capacitor 202, that could be characterized. The standard cell design and cell behavior information are stored in a standard cell library. Note that capacitor 202 can represent an output node capacitance of inverter 201 and/or capacitance of an exemplary wire connecting to another device. Thus, capacitor 202 can generically represent the load associated with inverter 201.
The standard cell library can include cell behavior information due to different loads. For example, if a cell is to be located a relatively long distance from its connecting device, then the effective load capacitance is large, and the standard cell library should have information related to the behavior of this cell with a large load. In reality, the relatively large capacitance can be due to the long wire that is needed (or at least anticipated) to connect to another device. A timing analyzer of the EDA tools will need this load information as input for timing analysis.
Additionally, a standard cell library can include standard cells behaviors due to different input slew rates. In general, an input signal provided to a device can affect its output signal. For example, referring to inverter 201, input signal 203 transitions from a logic high state to a logic low state, which generates an output signal 204 that transitions from a logic low state to a logic high state. The time a signal takes to transition from one logic state to another logic state is called transition time; and slew is the inverse of the transition time. Logically, the input slew can affect the output slew. In addition, input slew also affects other cell behavior/response such as the cell delay, which is defined as the time delay for the output signal to reach a certain voltage level after the input signal reaches a certain voltage level. This voltage level can be predefined, i.e. 50% of a power supply voltage.
Of importance, the timing constraints associated with a particular IC design may require selecting one cell rather than another cell to ensure system functionality. Therefore, the cell library must be able to generate a timing model for each cell. In a conventional standard cell library, a non-linear delay model (NLDM) is usually provided. In an NLDM library, the cell behaviors (such as delay and output slew) are modeled by lookup tables. The lookup tables usually use capacitance, input slew and etc., as indexes. Using these indexes, the lookup tables can be accessed and the delay/output slew associated with that cell can be determined using interpolation and extrapolation. Usually, interpolation accuracy is affected by the number and the positions of the index points. More points for each index and larger tables are needed to achieve high accuracy.
Note that a timing model is typically provided for each transition of a cell. That is, although one arc can be used for an inverter cell rise transition, a multi-input logic gate (e.g. a NAND gate) may use N arcs, wherein N is the number of cell transitions due to different inputs. An arc is the transition model of a cell due to different input slew and load capacitance. In the case of an NLDM model that supplies cell output slew and delay to the timing analyzer, each arc of a regular cell includes a cell output slew and a cell output delay lookup table. Further note that timing models can be provided for both rising and falling edges. Specifically, a device may have a different delay associated with receiving a falling edge (see, for example, input signal 203) versus receiving a rising edge. Typically, a standard cell library includes cell behavior information associated with both rising and falling edges.
Unfortunately, with the continuous down-sizing of semiconductor transistors, calculating cell delays and output slews using lookup tables providing cell output delay and output slew is becoming increasingly inadequate. Specifically, transistor behaviors are becoming more nonlinear and cell driving behaviors become too complex to model with just output slew and delay, thereby rendering the NLDM model inaccurate. To provide greater accuracy, another type of timing model that characterizes cell parameters over time was developed. This type of model is often known as the current-source models.
For example, referring to FIG. 2A, transitioning input signal 203 provided to the input terminal of inverter 201 results in certain cell responses, e.g. output currents and voltages over time. FIG. 2B illustrates an exemplary graph 210 showing the output current of device 200 over time, i.e. an I(t) curve. FIG. 2C illustrates a corresponding graph 211 showing the output voltage over time, i.e. a V(t) curve. FIG. 2D illustrates a corresponding graph 212 showing the output current versus the voltage, i.e. an I(V) curve. Because these curves can provide voltage and/or current information for the entire transition period, this type of timing model enables significantly more accurate timing analysis than the traditional NLDM timing model that only provides output delay and slew information for each transition.
Note that because of the known relationship between the I(t), V(t), and I(V) curves (i.e. I=C (dV/dt)), one curve may be converted to other curves. However, because the timing analysis methodology may work better with a certain type of curve, and because there is usually an accuracy lose in curve conversion, one type of curve may provide better timing analysis performance than the others. Therefore, different EDA vendors provide different timing models based on different curves. For example, Synopsys, Inc. provides a Composite Current Source (CCS) timing model based on I(t) curves. Cadence Design Systems provides an Effective Current Source Model (ECSM) based on V(t) curves.
To store an I(t), V(t), or I(V) curve, values associated with fixed sampled or adaptively sampled points on the curve can be placed in a database. A typical database may need 10-20 floating point numbers to represent a curve. For example, the I(t) curve f FIG. 2B can be represented using 9 adaptively sampled points (each point shown as a “*”), thereby requiring 9 time values and their corresponding current values (9+9=18. Other databases could include fewer or more floating point numbers to represent a curve. For each cell timing arc, multiple curves are needed for different input slew and load capacitance indices. For example, if 10 slew and 10 load indices are used, then the cell timing arc has 10×10=100 curves. Multiple arcs are also needed to model different type of cell transitions. To give an example, a standard cell library may have 1000 cells and each cell could have up to 10 or more transitions.
To facilitate designing current ICs and taking into account different input slews, load capacitances, as well as different cell transitions and different cells, a curve library might need to store up to 1 million or more curves. FIG. 2E illustrates an exemplary CCS library 213 including a plurality of curves stored as vectors. These curves may occupy more than 90% of the storage space of the library. Moreover, varying fabrication processes or temperatures may require multiple (5-20) libraries to be provided, thereby significantly increasing the size of an already large storage space. Moreover, EDA tools waste valuable memory and CPU time when loading large libraries.
Therefore, a need arises for providing accurate timing models for standard cells, as well as reducing the storage cost of storing curves in the standard cell library so that library storage space and EDA tool memory usage for loading the library can be substantially reduced.